Many integrated circuits are fastened to a lead frame which constitutes the metallic terminals for connecting the packaged integrated circuit to other circuits on a printed circuit board, or the like. Generally, a single integrated circuit chip is mounted to the lead frame and then encapsulated to form a packaged device. However, the prior art is replete with teachings of the integration of multiple integrated circuit chips into a single package. This allows multiple functions to be provided by a single packaged device. In addition, this compact arrangement reduces the space required for the package, as compared to several individual packaged devices, as well as reduces the pin count, again as compared to the number of pins that might be required of the multiple individual packaged devices.
The integration of multiple chips into a single package is not unlimited, as heat dissipation can be a factor, as well as the overall size of the package employed. JEDEC standards control the type of packages accepted by the integrated circuit industry. While large packages are available, manufacturers attempt to maintain the package size as small as possible to maintain competitiveness in the market, and increase density of the circuits on an printed circuit board.
In a typical integrated circuit package employing multiple chips, it is a common practice to mount the chips separately and provide interconnections between the chips using wires bonded to the pads of the chips. The contact pads of one or more of the chips can be soldered to the leads of the metallic lead frame. The assembly then undergoes a molding process where a liquified material is injected into a mold which, when solidified, provides mechanical protection to the lead frame and chips attached thereto.
There are different techniques for stacking integrated circuit chips together in conjunction with a lead frame. Some of the techniques are set forth in U.S. Pat. No. 6,919,627 by Liu et al; U.S. Pat. No. 6,897,565 by Pflughaupt et al; U.S. Pat. No. 6,890,798 by McMahon; U.S. Pat. No. 6,861,760 by Oka et al; U.S. Pat. No. 6,841,858 by Shim et al; U.S. Pat. No. 6,806,559 by Gann et al; U.S. Pat. No. 6,777,648 by Coomer; U.S. Pat. No. 6,759,737 by Seo et al and U.S. Pat. No. 6,753,207 by Hur.
It can be seen that a need exists for a technique for integrating multiple chips into an integrated circuit package without using bonding wires. Another need exists for a method of soldering chips directly together, and to a lead frame to simplify the integration process and to facilitate assembly thereof.